Realisation of parallel (p,q) counters for high-speed array multiplier

With current trend towards single chip digital signal processors and the growing demand for more powerful and real time performance of such processors, further improvements in speed would need to be made on conventional iterative carry-save array (CSA) multipliers. Considerable increases in the speed of array multipliers can be achieved by adding more than one partial product bit at a time by employing higher order parallel(p,q) counters. This approach heavily depends on an efficient realisation of a counter, which ideally should have a delay and complexity comparable to that of a full-adder. An iterative array multiplier which employs a (5,3) counter was recently reported and based on similar techniques, a novel array Multiplier utilising (2,2,3) counter cells was developed in this project. The study shows that both the (5,3) counter and (2,2,3) counter architectures are quite close to conventional array multipliers from a VLSI implementation point of view. Assuming the counters operate at a comparable speed as a CSA full-adder, the (5,3) counter scheme is faster than conventional array multipliers by nearly a factor of two, while the (2.2.3) counter technique offers significant improvements for large operand wordlength. In this work, the (5,3) counter and (2,2,3) counter were studied, principally on the efficiency of operation speed and the viability of the array architectures in the fast bipolar ECL technology. For this purpose, a reconsideration of threshold logic, in view of the better IC processes of today as well as the well-proven cascade ECL technique was investigated. A novel threshold circuit technique based on partial use of negative weighted inputs is proposed to overcome the maximum fan-in weight limitation found in traditional threshold circuits. A method of mapping a logic function onto series gated ECL suitable for software implementation is presented. The work also includes the design of a 16 X 16-bit Booth-encoded multiplier and a test chip composed of ring oscillators, using state-of-the-art bipolar technology. Simulation results show that the most efficient realisation is the (2.2.3) counter cell implemented in series gated ECL using well-proven gates. Circuit simulations indicate the (2,2,3) counter to be nearly as fast as a CSA full-adder. With such a realisation of the (2,2,3) counter cell, significant improvements in the speed of the (2,2,3) multiplier over that of conventional CSA multiplier can be expected, especially for large operand wordlengths.