Research On Reversible Logic Synthesis And Performance Analysis For Low-power Design Of Integrated Circuits

With shrinking device size,physical effects become an increasinglycritical determinant of synthesis,optimization and performance analysis inVLSI design.The increasing of circuits scale as well as the more prominentphysical effects bring huge challenge to the design of integrated circuit.ICdesign automation is a rapid development,changing,interdisciplinary andalgorithm-intensive fields,where exists lots of combinational optimizationproblems and statistic analysis problems.Therefore,it draws great concern ofthis yield.With technology scaling,process variations have a growing impacton circuit performance(such as speed and power) for today's integrated circuit(IC) technologies.Low power design automation tools have to consider theimpact of process variations.It needs more effectual circuit delay and poweranalysis algorithm.Advance analysis efficiency is interested in the yield and isbecoming a key issue in present and future technologies.Under these situations,this thesis investigates logic synthesis and performance analysis whichconsiders physical effects.It is hoped that these discussions presented in thethesis can push forward the research work on the low power design.The thesis analyzes the work property of reversible circuits,synthesis andoptimization problems as well as performance analysis problems.Also,itintroduces some practical design algorithms behind these problems.The thesisconsists of four parts,corresponding to various aspects of low power designissues.The first part analyzes the area and delay of reversible ciruits.Asymbolic synthesis algorithm based on the matrix model and symbolic algebrais introduced to solve computational complexity problem.The second partresearch works considering the crosstalk problem in the logic,synthesis.Anefficient crosstalk reduction algorithm by permuting wires is also introduced inthe thesis.The third part analyzes the delay and leakage power of reversiblecircuits under process variation.The fourth part investigates the hierarchicalperformance analysis.A performance-oriented parameter reduction method is presented.A performance analysis under time-space parameter is discussed.The main contribution of the thesis are as follows:The matrix modelof reversible circuit is defined.Using the model allowsus to easily extract the required factors of cost function and the inputs andoutputs values of each point in circuit.It minimizes the number of gates,pathdelay and crosstalk as the objective.We act the reversible logic synthesisproblem as multi-output logic synthesis.The method has greater potential to beextended to functions with more than just a few inputs and outputs.We resolveBoolean problem via symbolic algebra method.It not only solve computionalcomplexity,but also improve circuit performance.The heuristic Synthesis algorithm is presented in the thesis.We define thesimilarity between waveforms by statistics.Based on matrix model andsymbolic algebra,the thesis offers a symbolic synthesis method and performsdelay and crosstalk optimization simultaneously.Using the cost function themethod steers the synthesis process,which considers multiple optimizationobjectives,including area,delay and crosstalk.To solve low power problem,we not only use low power circuitconfiguration,but also combine with other design methods.The thesisconstructs improved quadratic model using Hessian matrix.We correct varianceanalysis result of existing quadratic model.Using the improved quadratic model,circuit delay and leakage power analysis under process variations is presentedand demonstrated.In the thesis,a hierarchical modeling for performance analysis is built.Circuit delay and the lognormal expansion of the leakage power areexpressed as the quadratic model.A novel parameter reduction method basedon CH(Correlation-Hessian matrix) is presented.It accounts for allcorrelations,from manufacturing process dependence,to high-level analysisto produce more accurate performance predictions.In the thesis,issues of reversible circuits synthesis and based onCorrelation-Hessian matrix hierarchical delay and leakage power analysis under process variation are investigated.This work is a typical research work in ICdesign automation field considering lower power design.It is also a goodreference for other researchers and designers working in the field.