Ground noise minimization in integrated circuit packaging and printed circuit packs

Due to suboptimal assignment of pins to grounds and signals, the ground noise problem in integrated circuit (IC's) packages either persists or compromises the design by forcing too many pins to be wasted carrying ground reference. In addition, current IC placement rules do not, in general, account for the effects the relative IC positions have on ground noise at the PCB level. This document proposes a new CAD technique for optimizing pin assignment at the IC package and printed circuit board levels to minimize ground noise using simulated annealing. Optimization techniques are used in which the objective function is the ground noise as determined by simulation of the IC package leadframe and the board level track interconnect. However, modeling and simulation methods currently employed are prohibitively expensive in terms of CPU time.;For this reason, two circuit models of the total interconnect are developed and used concurrently: one to provide accuracy and the other to ensure fast execution. The first captures the leadframe at the IC level or the entire network of multi-connected PCB-level IC's. In the former case, the circuit elements used to describe the leadframe include resistors and inductors only. In the latter, the total interconnect is described in terms of resistive, inductive and capacitive parasitic elements. From these the signal path di/dt values are determined using a circuit simulator. These values are then provided to the second, entirely inductive model in which the noise voltages across the ground path inductances are calculated using a set of real, linear equations.;Results at the IC package and PCB levels indicate the usefulness of the method. Using simulated annealing with a ground noise cost function has provided an observed 26-fold reduction in ground noise in a 208-pin IC quad flat pack (QFP) from an admittedly poor initial configuration. However, the same process was able to produce a 2.2-fold improvement when an intelligent initial pin assignment was used. Furthermore, these results came at a CPU cost of about 1200 seconds each on a SUN SPARC10 workstation. At the PCB level, a PCP containing 15 IC's was selected for ground noise optimization. Of the 15 IC's, five were singled out as targets for ground noise minimization. Of the five, one was a 64-pin QFP while the other four were 160-pin QFP's. Calculation of ground noise for this configuration involved 14 of the IC's on the PCB. A maximum ground noise threshold of 500mV was specified for the five target IC's. After about 5 hours (SPARC10), a solution configuration was found. The initial configuration produced a maximum PCB-level ground noise of over 900mV and after optimization, the maximum ground noise had dropped to below 700mV. However, for PCB-level optimization, the IC packages are invariant from iteration to iteration. Therefore, the optimization process is able to minimize that portion of the ground noise due to the PCB-level ground return path inductance. Prior to optimization this portion of the ground noise amounted to about 570mV. After optimization, this value dropped to just over 200mV. Ideally, such a board-level optimization would be conducted after each of the IC's of interest had been optimized at the IC-package level.