Predictive transient circuit simulations of charged device model esd events in system in package chips

This thesis focuses on obtaining circuit models to simulate the voltage stress experienced by the devices on integrated circuit components stressed by the charged device model (CDM) electro-static discharge (ESD) testers. The thesis presents a simple package modeling methodology that can be used to create a distributed model to simulate the voltage stress across internal circuit nodes or a lumped model that can be used to study the CDM reliability of primary input/output circuits on the chip. This thesis shows that three-dimensional (3D) EM simulation based package models may not be necessary, and that reasonably accurate results can be obtained using a simple 2D package extraction method. A method to model the on-die circuits and parasitic resistances of the power/ground busses is also presented. The circuit simulations were used to (a) study domain crossing circuits in single and multi-die packages, (b) study inter-die interface circuits in the stacked die and 3D integrated circuits (3DICs) that use through-silicon vias (TSVs), and (c) estimate the peak CDM discharge current for any integrated circuit component with minimal knowledge of on-die circuits. Both the simulations and measurement results are presented in this document. The simulation results agree with the measurement results from several test chips. Therefore, the methods presented in this thesis may be used to perform circuit simulations on an integrated circuit component model before the chip is manufactured to optimize the ESD protection network, or to find ESD weaknesses in the integrated circuit. This thesis shows that it is not necessary to use full sized ESD protection circuits at the domain crossing circuits and inter-die interface circuits. Small, secondary voltage clamps are sufficient if the primary current-carrying paths such as the ground and power nets are designed properly. Guidelines are provided for the design of power and ground nets and the size of the protection circuits to be used at the domain crossing circuits and the inter-die interface circuits.