Study On Reliability Of Re - Wiring Wafer - Level Package Board Drop

Electronic packaging is the third largest integrated circuit manufacturing field. With the rapid development of integrated circuit manufacturing technology, decreasing of the craft linewidth is becoming the biggest bottleneck restricting the development of integrated electricity to follow Moore’s law. The development of advanced packaging technology can not only meet the high density packaging demands, but also could follow the development of integrated circuits manufacturing process. Wafer Level Package (Wafer Level Packaging, WLP) makes Packaging, testing and dicing directly on a Wafer, which greatly improves the production efficiency. WLP are widely used in all kinds of portable electronic products for its smaller shape factor, excellent electrical properties and thermal performance and low manufacturing cost. Most of WLP devices are used in the mobile equipments, so the drop reliability tests are highlighted.Wafer level package(WLP) using redistribution techniques is an alternative approach that relocates the pads over the active area layer and integrates Passive Components, which offers a variety of advantages such as such as high density and low cost. Board level drop is conducted on WLP with RDL structure according to JEDEC standard (1500G,0.5ms). The change of daisy chain of samples was collected by high speed data collector and the transient failure time was recorded. The characteristic life of each group was calculated by Weibull statistics. The reliability of different RDL chip sizes (Pitch and ball size) is discussed in the article. The failure mechanism caused by drop shock of two Bump structures of RDL and copper pillar were explained in deep through Combining Finite element analysis (FEA) based on X-section sampling and topography characterization.The results of board level drop demonstrate that the most of device failure modes at the chip side located between bump and chip. Compared with traditional single chip package, wafer level package has coated a variety of thin lays on chip surface:buffer layer, under bump metallurgy layers, bumps, etc. The interface issues between layers become much more prominent. Therefore, the interface reliability of under bump metallurgy (UBM) layers was specifically studied by thermal test method. After high temperature aging and reflowing, the interface micro structure was characterized by surface morphology methods such as SEM, TEM, the growth behavior of the interface phase is analyzed and thermal stability of titanium adhensive layer was evaluated.