Study On Mixed-signal Circuits Power-noise Co-optimization Methods

With the increasing demand of portable products and embedded systems in information society, the integrated circuits is running towards ultra large-scale, deep sub-micro and mixed signal designs. The power consumption, as well as the noise in the circuit system is becoming greater and greater, and the correlation between noise and power consumption has been strengthened. Both the low power and low noise features have to be considered during integrated circuits design, which named as power-noise co-optimization design.The power-noise co-optimization design in mixed signal circuits consists of two parts, which are the power-noise estimation and the power-noise optimization. This dissertation summarized the previous works on digital circuits power estimation and optimization techniques, and pays special attention to the study on mixed-signal circuits' power-estimation. As an example, a power estimation analytic model of analog to digital converters has been established, which has the advantages of brief structure, and easily implemented in design tools. The experimental results exhibit this model can obtain high precision in power estimation.In noise estimation methods, the estimation models of cross-talk noise and substrate coupling noise have been established. The relative error between cross-talk noise estimation model and Hspice model is less than 8%, and the relative error between the estimated value of substrate coupling model and the estimation value of equivalent resistance-capacitance network model is within 15%. The computational complexity and the time for simulation of those two models are great less than other that of estimation methods. Even more detail elimination methods are proposed to overcome the cross-talk noise and substrate coupling noise.The power-noise co-optimization method of circuit architecture and the relation between device threshold voltage and circuit performance and power has been studied. In the case of speed performance non-decreased, a numerical method, which bases on circuit simulation, has been presented to find the optimized values of the operating voltage and threshold voltage in circuits. According to this method, the power-noise co-optimization design has been achieved.As an example, the power-noise co-optimization design on the circuit structure of a pipeline analog to digital converter has been carried out. The full differential timingsharing parallel architecture, OTA sharing and sample capacitance scaling techniques are adopted in the circuits design. Even more the multi-insulated technique is introduced in the key differential input pair transistors and switch capacitances. Based on 0.25um mixed-signal CMOS technology, the simulation of the whole design circuits has been done, the power dissipation is 23.3mW, under the condition of 2.5V operating voltage and 40M/s sampling rate, the die size of the chip is 1,6><1.0mm2. The design target of low power and low noise characters in the ADC is achieved, with high-speed and high-resolution features.The proposed works are innovative in the area of modeling and simulation of mixed-signal circuit power-noise co-optimization among proposed works at home and aboard. Not only the models established can be used in relevant simulation work directly, and the modeling course and method can be offered for modeling of other relevant problems.