Physics and technology of thin film silicon-on-insulator power MOSFETs

Power integrated circuit (PIC) technology has attracted increasing interest in recent years due to the numerous advantages of the monolithic integration of power devices with their control circuitry. The ability to implement superior dielectric isolation in silicon-on-insulator (SOI) material makes it attractive for PIC applications. Many of the well-known advantages of SOI material for logic devices such as fast switching, radiation hardness, and high temperature operation also extend to power devices. Unfortunately, it has proven difficult to achieve high breakdown voltage power MOSFETs without resorting to thick SOI films which complicates isolation.; In this work, a promising alternative which combines a linearly graded drift region doping profile with a sub-micron SOI film to achieve high breakdown voltages is investigated. A key finding is that power MOSFETs built in SOI can have on-resistance and breakdown characteristics comparable to lateral MOSFETs built in bulk silicon while retaining all of the advantages of SOI material.; The implementation of the linearly graded drift region profile is examined. A single masking step using a series of slits of varying width followed by an implantation and drive-in has been found to give profiles with excellent linearity.; Graded drift region MOSFETs were fabricated to investigate their characteristics and to compare with models. Excellent agreement has been found between measurements and models for both on-resistance and breakdown voltage. The highest measured breakdown voltage was B020V. Breakdown was found to be sensitive to the linearity and gradient of the drift region profile. The on-resistance of graded devices is higher than devices built in bulk silicon but the difference becomes smaller at higher breakdown voltages. The on-resistance can be reduced considerably by making simple modifications to the basic device structure.; Graded MOSFETs built in SOI layers less than 0.3 microns thick were found to have poor high-side characteristics due to pinch-off of the drift region. A dual SOI thickness structure has been found to have good high-side behaviour while avoiding the disadvantages of thicker SOI layers. The choice of an SOI and buried oxide thickness to achieve a given breakdown voltage is also examined.