Low-power digital signal processor architecture for multiple standard wireless communications

There are many different standards being developed and deployed all over the world for wireless communications. As the technologies in wireless communications and integrated circuits advanced, the popularity of wireless communications increased dramatically. The usage of different wireless communications standards started to overlap and create a need for an integrated environment across different standards. Multiple standard wireless communications is now in demand. In order to provide integrated service across different existing and new future standards, the hardware architecture should be flexible enough to process different wireless signals in different standards and also to accommodate future modifications of the standards. On the other hand, mobility is one of the primary reasons for the popular adoption of wireless communications applications. True mobility demands a long usage interval of mobile units. Therefore, low power consumption becomes another requirement in multiple standard mobile wireless communications. However, flexibility and energy efficiency have been recognized as conflicting factors. This imposes a severe dilemma on the system architecture for multiple standard wireless communications.;This dissertation presents new innovations that can be used to mitigate the tradeoff between programmability and power consumption in the environment of wireless communications processing. First, a new low power reconfigurable macro-operation signal processing architecture is presented. This architecture can be used to reduce the power consumption of computing engines inside the mobile units. Second, a unique low power signal processing arrangement and method for predictable data is presented. This novel approach deviates from current one instruction stream architectures to a two instruction stream architecture. This provides a more efficient structure for data management specifically for wireless communications processing. Then, a new overall system architecture is described to make efficient use of the inventions mentioned above. A new register file architecture is also introduced to merge the functionalities of microcontroller and digital signal processor. This further reduces overhead from the communications and data transfers that would be required between two different processors. Representative routines extensively used in wireless communications processing are simulated. Compared with conventional programmable processor architectures, up to 55% power reduction and up to 37% latency reduction are achieved by the proposed architectures.