A design methodology for highly-integrated low-power receivers for wireless communications

Due to its potential to offer ubiquitous information access, wireless connectivity is playing an increasingly significant role in communications systems. The success of future wireless systems will depend heavily on their ability to provide high capacity while maintaining low cost, small form factor, and low power consumption in the portable devices. However, many existing commercial transceivers are expensive, consist of a large number of discrete components, and exhibit moderate to high levels of power consumption. One possible explanation for these inefficient solutions lies in the historically unilateral relationship between system designers and hardware designers. An efficient solution requires a design strategy which tightly incorporates implementation issues throughout the process of defining the system specifications.; This thesis describes a design methodology which facilitates the evaluation of tradeoffs between implementation issues and overall system performance, focusing primarily on the receiver as an example. First, system-level specifications, such as modulation scheme and signal bandwidth, strongly influence the choice of receiver architecture, which in turn, has ramifications on the achievable power consumption and integration level. When system-level specifications are determined without considering their impact on receiver architecture selection, single-chip solutions may be very difficult to achieve or just simply infeasible. Based on system-level considerations, guidelines are presented for the selection of receiver architectures, including the heterodyne, direct-conversion, image-reject, and low-IF topologies.; Second, the rapid improvements in digital CMOS technology provide an opportunity to use advanced digital signal processing algorithms which in the past were considered too complex to implement in the mobile device. These algorithms promise significant increases in system performance but their performance may ultimately be limited by analog circuit impairments, such as noise and distortion. This thesis describes the detrimental effects of a number of these impairments and presents a system-level simulation framework which facilitates the direct evaluation of these effects on the performance of digital communications algorithms. The simulation framework is implemented in Simulink, which offers compatibility with MATLAB, a simulation tool already widely used for the development and evaluation of communications algorithms. This simulation framework relies on baseband-equivalent models for all of the RF building blocks in order to avoid simulation at the carrier frequency, resulting in faster simulation times.; These strategies are then applied to the design of a high-speed wireless downlink for an indoor picocellular system. The system provides an aggregate data rate of 50 Mb/s with a transmission bandwidth of 32.5 MHz and a carrier frequency of 2 GHz. The wide bandwidth of the desired signal facilitates the use of a direct-conversion architecture. A receiver prototype is implemented to meet the specifications determined from the system-level simulations. A power-efficient solution is achieved by taking advantage of the relaxed specifications as well as by using low-power circuit implementation techniques. This receiver prototype includes the low-noise amplifier, frequency synthesizer, mixers, baseband amplifiers and filters, and analog-to-digital converters, all implemented on a single chip with a power dissipation of about 100 mW.