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The monolithic integration of enhancement- and depletion-mode high electron mobility transistors for low-power and high-speed circuit applications in the lattice-matched indium phosphide material system

Posted on:2000-08-28Degree:Ph.DType:Dissertation
University:University of Illinois at Urbana-ChampaignCandidate:Mahajan, AadityaFull Text:PDF
GTID:1468390014963367Subject:Engineering
Abstract/Summary:
The need for transistors that can operate at millimeter and microwave frequencies has increased due to a burgeoning consumer market, which has created a niche for compound semiconductor devices, including InP-based high electron mobility transistors (HEMTs). These devices have demonstrated the highest unity-current gain cutoff frequency to date as well as the lowest noise figure of any transistor. However, to date, only depletion-mode HEMTs (D-HEMTs) have been available to the circuit designer. As a result, traditional technology such as buffered FET logic (BFL) or source-coupled FET logic (SCFL) has been employed, which can be quite complex and dissipate large amounts of power.; By using a buried-Pt process in conjunction with proper heterostructure design, a procedure for the fabrication of enhancement-mode HEMTs (E-HEMTs) has been developed. Following the full characterization of E-HEMT devices, a heterostructure was then designed for the monolithic integration of E-HEMTs and D-HEMTs, using a two-level etch-stop process. Devices were successfully fabricated and characterized which showed the viability of a directcoupled FET logic (DCFL) circuit technology in the InP material system. To demonstrate the feasibility of this technology, DCFL ring oscillators were fabricated and tested. These circuits successfully demonstrated high-speed, low-power performance while utilizing only a single voltage supply.
Keywords/Search Tags:Transistors, Circuit, FET logic
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