| With CMOS technologies marching into very deep sub-micron region, the manufacturing variations are becoming an important issue in both design and yield improvement. Unlike device variations, whose impact on circuit timing can be captured by worst-case comer point methods, the impact of interconnect variations is context-dependent. Physical design details have to be taken into account if an accurate estimation on the impact of the variations is needed. However, at this stage, the overwhelming data volume and the complicated physical phenomena make the existing methods either inaccurate or inefficient. In this dissertation, we propose a novel deterministic variational order-reduction method. By combining the state-of-the-art interconnect order-reduction techniques and matrix perturbation theory, the method generates a reduced-order model with direct inclusion of the manufacturing variations. By applying this method, the impact of some key statistically-independent process variations, which have the most significant systematic effects on timing performance, can be analyzed in a more realistic, context-dependent manner.; To demonstrate the application of this analysis methods, as well as the effects of the interconnect variations on the IC timing performance, the impact of interconnect variations on the clock skew in a leading-edge industrial design is analyzed. The results show that the interconnect variations alone can cause up to 25% variation in the clock skew, which might be a significant problem for the circuit performance.; With the application of variational reduced-order model, another important issue for statistical analysis is the efficient simulation of the interconnect models. Because the reduced-order models are mostly in frequency domain, a frequency-to-time domain conversion is needed in order to incorporate the model into a timing simulator. In this dissertation, we also propose a frequency-to-time domain method which can achieve the highest possible accuracy under the piece-wise linear waveform assumption while maintaining high efficiency. Moreover, we propose a method to expedite the simulation of RC interconnect model by sparsifying the time domain stencil. Such a method is useful for interconnect networks with large number of ports, such as a clock tree. |
