Post-silicon timing diagnosis under process variations

In this thesis, we propose a framework for automating post-silicon timing diagnosis under process variations. Our framework can isolate the failing paths in "slow" chips that fail to operate correctly at the required frequency, and localize those segments on the failing paths that show more deviation in their post-silicon delays.;The first step in our framework is to identify the statistically-critical paths under process variations that have the highest probability of failing their frequency requirements in the presence of process variations. We first define a "violation probability" for each gate or interconnect in a circuit, which measures the likelihood that a particular gate or interconnect forms part of a statistically-critical path. We then compute lower and upper bounds on the violation probability for an arbitrary segment of consecutive gates and interconnects. These bounds are further used to help identify those statistically-critical paths accurately and efficiently.;Next, we aim to isolate those "failing paths" that cannot meet the required timing constraint. This is done by predicting the post-silicon delays of the statistically-critical paths using those of a few representative paths. To identify these "representative paths", we take advantage of the fact that the delays of the statistically-critical paths are highly correlated, due to the large number of overlaps among these paths, and the spatial correlation among process variations. Simulation results show that we can predict the timing of a few thousand statistically-critical paths from the delays of around 100 representative paths.;Finally, we formulate an optimization problem to diagnose those segments on the failing paths that show a large deviation in their post-silicon delays. It forms segments that maximize a defined metric referred to as "diagnostic resolution". A high diagnostic resolution indicates that the chosen segments are likely to have a post-silicon delay larger than their design-time estimates. Simulations show that our proposed procedure is computationally efficient. It can yield a high diagnostic resolution, and further accurately rank these segments in order of their delay deviations.