A fast timing simulator with accurate reduced-order interconnect models

In this research, we investigated techniques to simulate RLCG interconnects along with driving/terminating nonlinear circuits with high computational efficiency. Existing fast timing simulators have the shortcomings of inadequate modeling of interconnect loading and lack of inductive effects. Especially with shrinking device sizes the interconnects are playing a more important role than ever. It is a well accepted fact that interconnect lengths are not going to decrease; hence, interconnect delays will dominate over gate delays. Furthermore, a paradigm shift of putting the interconnect design ahead of logic design is currently being discussed in academia. Considering these facts, it is very appropriate to address circuit-level interconnect simulation techniques. In our research, model-order reduction and simulation techniques are built on the analytical solution ideas of generic circuit primitives for computational efficiency reasons.; Two methodologies are proposed to simulate interconnect networks in our simulation environment. In the first technique, the RLC( G)/RC(G) interconnect networks are reduced to a predetermined circuit model, e.g., L, π, etc., through moment matching techniques. This model is then incorporated into the generic circuit primitive and solved analytically to obtain the unknown node voltages. Although this method serves the purpose of efficiency and reasonable accuracy, it may result in unstable realizations. To address the stability and passivity issue, an interconnect model-order reduction technique without a predetermined circuit model is proposed. This technique guarantees passive reduced-order models by introducing the concept of moment component matching. It is applied to obtain orthogonally and congruently diagonalizable reduced-order models by matching the impedance parameters of the reduced-order model to those of the original interconnect.; The methodologies and techniques developed in this research are implemented in a fast interconnect/timing simulator, ILLIADS-I. In their practical implementation the robustness of the interconnect models is further improved to achieve absolute numerical stability in addition to their theoretical passivity and stability. Unlike other approaches, the interconnect simulation methods in ILLIADS-I do not handle the interconnect network separately for obtaining and then placing a corresponding stamp into a SPICE-like simulator. The accuracy and speed have been demonstrated for a number of circuits for various loads and input waveforms. Experimental results show that ILLIADS-I is both accurate and fast. The speed advantage is shown to increase with the circuit size for multilevel interconnect networks with nonlinear driver and load circuits. In addition to ILLIADS-I, a stand-alone linear interconnect simulator called iPINTA (Illinois Passive Interconnect Analyzer) has been developed. This simulator is a complete tool for analyzing linear multiport interconnect networks based on interconnect simulation principles described in the thesis.