Modeling Of Cell Nongaussian Delay Distribution And Timing Analysis

With the improvement of circuit integration,the time consumption of the "gold standard" Monte Carlo simulation is becoming unacceptable,and Statistical Static Timing Analysis(SSTA)can accelerate circuit timing analysis.However,under low voltages,process parameter variations cause circuit delay to exhibit a non-Gaussian distribution,and traditional SSTA models(such as Skew Normal model(SN))become less accurate.Therefore,considering the influence of process variation parameters under low voltage,this thesis establishes an accurate non-Gaussian distribution model of circuit delay.Based on the numerical modeling method,a Double-level Skew Normal Density Estimation(DSNDE)model is proposed on circuit delay.The DSNDE model includes two steps: In the first step,the Probability Density Function(PDF)of cell delay is expressed as a skew normal distribution form,and parameter estimation is performed according to Monte Carlo simulation data.In the parameter estimation stage,in order to improve the convergence speed and accuracy,genetic algorithm is used to improve the maximum likelihood estimation optimal parameter selection process.In the second step,the cell delay PDF is used as input to calculate the discrete distribution of path delay according to the block-based timing analysis method.In order to improve the accuracy of the path-/+3sigma delay,a second level of skew normal density estimation is used to predict the path delay PDF for the discrete distribution.Combining the discrete distribution of the path delay and the delay PDF,the-/+3sigma delay is estimated.In this thesis,SMIC 28 nm is used to simulate and verify the DSNDE model at the cell and path levels under 0.5V and 0.7V,respectively.An inverter,a NAND gate,and a NOR gate are taken as cell circuit examples,and ISCAS85 benchmarks are taken as path circuit examples.The results show that: On the cell,when the operating voltage is 0.7V,the average relative error of DSNDE on-/+ 3sigma delay is 1.36%/1.45%;when the operating voltage is 0.5V,the average relative error of DSNDE on-/+ 3sigma delay is 3.62%/6.19%.On the path,when the operating voltage is 0.7V,the average relative error of DSNDE on-/+ 3sigma delay is2.47%/2.65%,and the accuracy is improved by 16% / 67% compared to SN;when the operating voltage is0.5V,the average relative error of DSNDE on-/+ 3sigma delay is 3.82%/3.85%,and the accuracy is improved by 9%/63% compared to SN.