High frequency noise in CMOS low noise amplifiers

This dissertation explores the physical origin and contributing mechanisms of noise in MOSFETs, as well as a design methodology to minimize the impact of noise on fully integrated LNAs. Investigating the physical noise sources in the MOSFET imposes significant computational requirements, due to the multi-dimensional nature of the device and higher order transport models. This dissertation presents a quasi 2-D noise simulation technique which provides an accurate and fast solution for MOSFET noise analysis.; The physical origin of the excess noise in short channel MOSFETs has been identified. Source-side contributions dominate drain current noise; non-local transport behavior causes higher local ac resistance near the source junction and in turn generates extra noise contribution which is amplified by the channel transconductance. This phenomenon is directly reflected in excess noise in scaled submicron MOSFETs. Higher order transport models are essential to capture this effect in noise simulation.; Contrary to the common assumption that drain current exhibits only flicker and white channel thermal noise contributions, this study demonstrates that the substrate generates thermal fluctuations that produce additive channel noise, amplified by the substrate transconductance. This component produces another plateau and frequency dependence in the noise spectrum of the drain current. Moreover, the effect tends to exaggerate the drain noise factor at low frequencies.; The high frequency noise modeling for MOSFET devices generally requires at least three parameters. This study demonstrates that while two-parameter approaches lead to errors, the results do not cause noticeable discrepancies for most practical circuit topologies. The modeling approach used in BSIM4 has been independently validated and is shown to be sufficient in capturing the physical origin of the excess noise.; Explicit guidelines for LNA design have been presented based directly on measured noise parameters and two-port noise theory. An 800MHz LNA test chip has been designed based on the proposed methodology. It achieves about 0.9dB of noise figure, which is competitive with that of GaAs and bipolar LNAs and also quite close to the values predicted using the analysis presented in this work.