Research On FinFET Device Modeling Technology

Due to the gradual reduction of the transistor's feature size to the nanotechnology node with the vigorous development of integrated circuit technology,its small size effect has become more and more obvious,and the further scaling of the device size has been limited.Therefore,to break the limitations of semiconductor technology,a new type of multi-gate device structure FinFET is proposed.Compared with MOSFET,FinFET has stronger gate control ability,can better suppress short channel effect(SCE),reduce leakage current,and can greatly improve chip processing speed and greatly reduce power consumption.Besides,FinFET has good compatibility with CMOS process.Based on these advantages,many semiconductor manufacturers began to move into the FinFET process,which including Intel 22 nm,14nm,TSMC 16 nm,10nm and 14 nm of GLOBAL-FOUNDRIES.With the continuous expansion of FinFET process applications in the semiconductor field,the research on FinFET process model has become increasingly important.Moreover,traditional planar models cannot accurately characterize the physical characteristics of 3-D FinFETs,so device modeling research faces new challenges.Therefore,it is necessary to establish device model which is suitable for the multi-gate 3-D FinFET process.In this thesis,the 14 nm silicon-based FinFET modeling and physical parameter extraction technology are studied.The main research contents of the article are summarized as follows:(1)The structure classification,working principle,device advantages,and performance optimization of FinFET are briefly explained.Then some typical physical effects in FinFET models are introduced.In addition,in-chip testing of devices and measurement results are briefly introduced and analyzed.(2)Considering the inaccuracy of the traditional open-short de-embedding method,the deep submillimeter wave de-embedding method combined with measurements and calculation is used for de-embedding,and then the small-signal equivalent circuit model after de-embedding is established.This model considers channel length modulation effect,non-quasi-static effect,and substrate loss and coupling effect.From 0.2 GHz to 50.2 GHz,the comparison between the model calculation results and the measurement data shows that the magnitude root-mean-square-error(RMSE)of S parameter of NF=6 transistor is less than 0.0095,while that of S parameter of NF=8 transistor is less than 0.0082.(3)Consider that some physical parameters are not uniformly distributed in energy or space and can have a significant impact on device performance.Therefore,in order to better predict the performance of the device,a physical parameter extraction method based on flicker noise test data is proposed.After the physical parameters are extracted based on the noise power spectral density of the test data,a flicker noise model is established to improve the accuracy of the extracted physical parameters.After that,the extracted physical parameters were further verified in the DC model.The physical parameter extraction method proposed in this paper can be used to accurately characterize the physical parameters of the prepared device and provide a reference value for the physical performance of the device for circuit design.