Mixed circuit and device simulation for analysis, design and optimization of optoelectronic, radio frequency and high speed semiconductor devices

Technology Computer Aided Design tools have played a vital role in the development of next generation semiconductor devices. Unfortunately, modern high speed devices can no longer be studied without considering parasitic components and biasing circuitry. These factors are especially significant for opto-electronic, radio frequency, and high speed devices whose performance depends on their interconnect, layout, and parasitic components.; This work describes the application of device simulation to opto-electronic and high frequency device design. It begins with a discussion of the tool development for such simulations. Two approaches are addressed. In the first approach, the device simulation is included in the circuit simulation as a numerical device model. The previous work of others is extended, addressing larger problems in terms of the number of devices, complexity of the devices, and parallel execution algorithms. A second approach reduces a linear circuit to a set of boundary conditions applied to the device simulator and thus allows for the inclusion of parasitic components during dc, ac, and transient analysis. In addition to circuit boundary conditions, an harmonic balance solver is integrated with the device simulator to allow for large signal RF simulation.; With these improvements to a device simulator such as PISCES, examples are provided to demonstrate the modeling methodology and tool capabilities. LED's for optical communication systems are studied and optimized. The impact of the layout is characterized for a MESFET used in RF communication circuits. The physical phenomena of poly-depletion in digital CMOS scaling is studied through mixed circuit and device simulation.; An in-depth example explores the analysis, modeling, design, and optimization of RF LDMOS transistors. A brief review of the device operation is provided and key modeling regions and methodologies are explored. The model is verified using measured I-V data and C-V characteristics and the RF simulation accuracy is evaluated by generating curves for gain, efficiency, and linearity. With a proven RF model, the transistors's RF performance is studied, the effect of parasitic components is analyzed, and design optimization is considered.