| High dielectric constant (high-k) insulators and metal gate electrodes are important for advanced MOS devices to limit gate leakage by increasing gate capacitance with ultimately thicker films and eliminate poly-depletion & dopant diffusion, respectively. Reactions between dielectric/substrate and gate electrode/dielectric during deposition or post-deposition processing lead to an increase in interfacial layer formation, and the mechanisms that control the changes need to be well understood. We investigate yttrium-based and hafnium-based high-k dielectrics and ruthenium-based gate electrodes formed by various processing methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD) on Si(100). Characterization techniques include IR, XPS, TEM, EELS, AES, and IV and CV electrical analysis. During deposition and post-deposition treatments the interfaces have some extent of interfacial layer formation. The extent of the intermixing depends on substrate surface preparation, process conditions, and annealing conditions. The transition metal alluminate dielectrics show evidence on flatband voltage tuning via charge compensation. Also, the ruthenium gate electrodes show that process condition can have a direct effect the electronic and chemical properties of MOS structures such as in-situ versus ex-situ capacitor fabrication and the role of subsurface adsorbed oxygen in ruthenium. |
