| A PLL frequency synthesizer used for high-speed data transmission is required to rapidly hop between frequencies. The fundamental problem is that the settling time is inversely proportional to the loop bandwidth, and increasing the bandwidth causes stability problems for the circuit due to noise interference. In this research, we demonstrate the feasibility of replacing the analog integrator in the loop with a digital adder and RAM circuit. This circuit has three advantages: (1) the hopping speed is greatly increased by the replacement of the analog integrator with digital; (2) the system is adaptive and can compensate for temperature drift in its components; and (3) the digital circuitry provides lead compensation to assure system stability. The circuit is designed, built and tested with both discrete chips and with a programmable logic device. We demonstrate that the loop will lock with the digital integrator circuit. In addition, a robust stability analysis is performed for this system. The analysis shows that the circuit is stable for a practical range of parameter values. |
