| A Field Programmable Gate Array (FPGA) is a reconfigurable integrated circuit (IC) which is a hardware platform for implementation of any digital design. Due to the reconfigurability of FPGAS, different designs can be mapped into the same device. Manufacturing (application-independent) testing of FPGAS requires a number of test configurations and test vectors in order to guarantee the functionality of the chip for all possible configurations. In application-dependent testing, the chip is tested only for a particular design.; Most of the transistors and the silicon area in FPGAS are used for the interconnection network. Most defects are in the interconnects. The focus of this dissertation is on the testing of interconnects, as there are already effective techniques for testing logic blocks.; The quality of test is measured by fault coverage, which is the ratio of the number of detected faults to the total number of faults. An efficient algorithm for computing the fault coverage of given FPGA test configurations targeting interconnect faults is developed. Compared to conventional methods, this technique is orders of magnitude faster and is able to report all detectable and undetectable faults.; For manufacturing testing, an automatic configuration generation method is presented. To test interconnects of application-dependent FPGAS, the programmability of the logic blocks are exploited. Various automatic test generation methods for a variety of fault models are developed. These methods result in a proven minimum number of test configurations. Also presented are high-resolution fault location schemes for both manufacturing and application-dependent testing.; A resistive open defect is an imperfect circuit connection which is modeled as a resistive connection. Techniques to test for and diagnose resistive open defects that exploit the programmability of FPGAs are presented, which can be used for both manufacturing and application-dependent testing. Using this technique, the delay of a defective path is increased several times more than the delay of the same fault-free path, resulting in a higher resolution in detectability, even at lower tester speed. |
