Novel high-speed & multi-function CMOS signal processing circuit

A transient waveform digitizer circuit with continuous sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 mum CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample storage, and attains 2 GHz sample speeds with up to 2 GHz analog bandwidth. Sample clock generation adopts a semi-synchronous approach, combining a phase-locked loop for highspeed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sample voltage levels are compared against reference levels that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample wide windows against up to 72 programmable patterns in real-time using a programmable logic array. Each trigger window is 8 samples-wide, overlapped sample by sample in a circular fashion through the entire 128 sample array. A trigger is flagged within 15 ns if there is a match, after which on-chip digitization can proceed via 128 parallel 10-bit converters. With these systems, this new device is a high-performance yet inexpensive means of detecting a transient signal event whose arrival time is not known beforehand.;The primary original advance that this dissertation demonstrates is the use of a real-time trigger system which acts as an "on-chip oscilloscope". It constantly watches the incoming signal, looking for signals containing specific signatures, after which only those signals are kept and digitized. This programmable, selective on-chip trigger system reduces data demands of the instrumentation system as a whole, perhaps by several orders of magnitude.;Another advance in this device is the first use of a phase-locked loop to generate a very high-speed internal clock from a lower speed external reference clock. Previous ATWD-type systems were fully-asynchronous, which is prone to drifting and voltage and temperature-related variations. Our semi-synchronous technique locks the sampling to an external clock, preventing drifts, while eliminating the need to supply and distribute very high speed system-level clocks.;In collaboration with the Physics and Astronomy Department at U.C.I., this technology has seen experimental use at the Ross Ice Shelf in Antarctica, and in tests has collected radio signals bounced from the bottom of the ice shelf.