| Recent advances in complementary metal-oxide-semiconductor (CMOS) devices have made this technology attractive for high frequency analog applications, such as wireless systems. This is because CMOS technology is cost effective, offers high levels of integration, and can be used to provide single chip solutions where digital and analog blocks are realized on the same chip. Although CMOS technology down-scaling improves the noise performance of MOS devices, as the size of these devices continue to shrink, modeling of their noise becomes increasing more complicated.; This thesis provides analytical solutions for characterization and modeling of high frequency noise of MOSFETs and develops ideas on using those solutions in the design of low-noise radio frequency (RF) integrated circuits (ICs). The discussion begins with a critical review of recently proposed models for the thermal channel noise, which is the main source of high frequency (HF) noise in MOSFETs, and continues to develop an analytical expression to model this noise.; To fully characterize the HF noise performance of MOS devices, compact expressions that can accurately predict the noise parameters of the MOSFET are developed. These parameters are minimum noise factor, Fmin , equivalent noise resistance, Rn, and optimum noise source admittance, Yopt. The accuracy of the expressions is verified with measured noise data obtained from short-channel MOS devices using a scattering and noise measurement system.; A noise parameter determination method to estimate the noise parameters of the MOSFET from a single noise figure measurement is developed in the third phase of this research. This method can be used to determine the noise parameters from measured noise figure of the device with a constant source impedance, e.g. 50 Ohms, after the scattering parameters of the device are measured. Experimental results are also used here to validate the proposed method.; Finally, optimum design of narrow-band RF CMOS low-noise amplifiers (LNAs) is discussed in the fourth chapter of this thesis. The design methodologies presented in that chapter are based on analytical formulations developed in the first three chapters of this work, and give insight to circuit designers to optimize the overall performance of LNAs, in terms of their gain, noise figure, and linearity, by properly designing the input matching network. Two LNAs are designed and measured to validate the proposed methodology. One LNA is designed for low-power operation and the other is optimized for the best overall performance. It is shown that significant improvement in the performance of the LNAs can be achieved by proper design of their matching network depending on the targeted application. |
