Reliability Of SiC Power MOSFET Based On Low-frequency Noise

Due to its superior properties,silicon carbide?SiC?has become one of the most advantageous semiconductor materials for further increasing power density,system switching frequency and power electronics system efficiency.In the last two decades,with the continuous improvements in material fabrication technology,SiC power MOSFET has been widely used in power electronic equipment.SiC power MOSFETs may suffer from reliability problems in applications with extreme operating conditions,such as reduced mobility and performance degradation,which can affect the reliability of device and system operation.Therefore,the degradation regulation and reliability of SiC power MOSFET under extreme operating conditions need to be further explored.In this paper,the reliability of the device under different stress?SC,TLP and UIS?was investigated based on electrical characteristics and low-frequency noise?LFN?.The main research work and results of this paper include:?1?The electrical characteristics and low frequency noise of SiC power MOSFET under short-circuit stress are discussed.The experiment results show that the on-state resistance and threshold voltage increase significantly.Meanwhile,the drain-source current decreases obviously with the increase of the SC cycles.Furthermore,the gate-source leakage current of the SiC power MOSFETs increases greatly and the blocking characteristics deteriorated after1000 SC cycles.The positive shift was observed on the gate-capacitance versus gate-voltage curve,which shows that the damage region could be in gate oxide of channel region after SC stress.The LFN results show that the trap density increases with the SC cycles.The physical mechanism be attributed to active traps generated at SiC/Si O₂ interface and oxide layer due to the peak ionization rate,the perpendicular electrical field and high temperature during SC stress.In addition,the released activation energy from the N atoms remaining in the device under oxidation reactions,which can cause fluctuations in the number of carriers and resulting in low-frequency noise.?2?The reliability of electrostatic discharge of SiC power MOSFET was investigated by TLP test.The experiment results show that the on-state resistance and threshold voltage decrease significantly.The gate-source leakage current of the SiC power MOSFETs remain stable.Meanwhile,the drain-source current increases obviously with the increase of the TLP cycles.The negative shift was observed on the gate-capacitance versus gate-voltage curve,which shows that the damage region could be in gate oxide of JFET region after TLP stress.The LFN results show that the trap density increases 4 times after TLP stress.The mechanism be attributed to the electrons tunnel to the conduction band due to the strong electric field of the gate,the electrons are accelerated by the electric field and collide with the Si O₂ lattice,the Si-O bond and Si-C bond were broken,oxygen vacancies and carbon vacancies are generated,which cause the increase of trap density and the degradation of electrical characteristics.?3?The degradation of electrical characteristics and low frequency noise of SiC power MOSFET under UIS stress are investigated.The experiment results show that the on-state resistance increases significantly after UIS stress.However,the threshold voltage remains stable.The drain-source current decreases with the increase of the SC cycles.The gate-source leakage current of the device increases 5 times.The negative shift was observed on the gate-capacitance versus gate-voltage curve,which shows that the damage region could be in gate oxide of JFET region after UIS stress.The LFN results show that the trap density increases 2.4 times.The mechanism be attributed to the peak electric field and the impact ionization rate of the gate oxide layer in JFET region during the UIS stress,the defects of electrical activity were generated and the defect density increased.At the same time,due to the vertical electric field,the holes are injected into the gate oxide layer in the JFET region of the device during the stress,which causing the degradation of electrical characteristics.