UDP/TCP/IP packet processing using a superscalar microprocessor

The bandwidth of communication channels has increased dramatically in recent years due to the introduction of fiber-optic links. Organizing and processing the data that is being transferred over these high performance communication networks has become a major obstacle. This research addresses the issue of UDP/TCP/IP processing overhead in an Instruction Set Architecture (ISA). The research will define the processing overhead and develop architectural enhancements to improve performance. The research contributions are divided as follow: (1) Developed a UDP/TCP/IP packet handling program that can be executed by a single CPU as a protocol processing benchmark. The program performance and functionality was validated using a commercial UDP/TCP/IP program. (2) Developed and implemented a superscalar processor simulator JAESS that can execute the UDP/TCP/IP protocol stack program from the previous task as an evaluation platform. In addition, an analytical method to validate superscalar processor performance was developed. (3) Characterize UDP/TCP/IP packet processing overhead where the simulated results showed excessive memory instruction execution while the overall instruction execution pattern varied insignificantly for different protocols, UDP/IP or TCP/IP, and packet sizes, 512 or 1024 byte packets. (4) Developed and evaluated the Precise Out-of-order Memory Execution (POME) method to improve memory instruction processing.