Quantitative Analysis On The Impact Of Memory Access Behavior By Instruction Dynamic Scheduling

The dynamic scheduling technology of instructions in the superscalar processor can effectively reduce the stall of the pipeline during sequential processing,improve the parallelism of instruction,and improve the performance of the processor.However,the dynamic scheduling of instructions also changes the execution order of the memory access instructions,destroys the locality of the memory access,and improves the missing rate of the D-cache.In addition,the speculative execution of the load instruction also creates a violation,bringing a replay penalty.This thesis modifies the gem5 simulation platform source code and quantifies the factors affecting the D-cache miss rate and the replay penalty caused by the violation of load instruction.This helps to understand these mechanisms and provide reference for processor design.In the study of the influence of dynamic scheduling on the D-cache miss rate,this thesis first demonstrates the inapplicability of the stack distance theory in predicting the D-cache miss rate of out-of-order processors,and then deeply analyzes the factors affecting the memory instructions.The simulation results of 14 SPEC2006 test programs show that the store-to-load forwarding mechanism has a limited impact on the D-cache miss rate because the probability of occurrence is less than 6.5%.In the scheduling methods of conservative,store sets and blind,the non-blocking issue mechanism combined with the speculative execution of load instruction increases the D-cache miss rate by 1.839,2.085,and 2.064 times,respectively.While these influencing factors increase the D-cache miss rate,they also reduce stall and ‘bubbles' in the pipeline,improving processor performance,so modern superscalar processors still use these mechanisms.When studying the influence of dynamic scheduling of instructions on CPI,the simulation results of 14 SPEC2006 test programs show that in the three modes of conservative,store sets and blind,the average performance of the processor has been improved by 1.514495,1.708431,and 1.708162 times,compared with the sequential.The research in this thesis also finds that the replay penalty of the violation caused by the load instruction is concentrated in 11 to 13 cycles,and the penalty time is smaller than the total CPI,the maximum is less than 5%.With the increase of ROB,IQ,and SQ,the violations of load instruction gradually increase,and the penalty time for violations also increases.However,due to the decrease of steady-state CPI,the trend of total CPI in different programs is also different.