Instruction-level Parallel Processing Technology

ILP (Instruction-Level Parallelism) is a technology to enhance the processor performance by increasing the number of instructions executed per clock cycle. VLIW (Very Long Instruction Word) processor exploits ILP mainly using static schedule by compiler, while having much simpler hardware implement, it requires intelligent compiler and it is hard to provide compatibility. On the other hand, superscalar processor exploits ILP mainly using dynamic execution mechanism, although gaining wide application, it is hard to enhance the performanbe even further with complex hardware implement. EPIC (Explicitly Parallel Instruction Computing) is a new ILP technology taking advantages of both superscalar and VLIW, it enhances the performance using both hardware and software with synergy between them. The joint HP-ontel?s IA?4 ISA (Instrdct ion Set Architecture) is the first instance of commercially available microprocessor based on the EPICO This paper presents the development and the features of VLIW and superscalar processor with brief comparison between them; analyzes the key causes for preventing ILP: data dependence, control dependence and resources conflicts; discusses the instructionssue policy of superscalar processor; and explains dynamic execution mechanism of Pentium III. Combining EPIC features and programs as example, this paper also analyzes the ILP techniques used by IA?4 ISA: instruction coding, predication, data speculation, control speculation and software pipelining, etc. This paper concludes that the ILP technology will play even more important roles in enhancing processor performance. But IA?4 ISA still has its limitation, it needs the support of intelligent compiler and has to solve the problem of compatibility with IA?2 instruction set.