CMOS I/Q down-converter operating at 2GHz for wireless communication receiver

The goal of this research is to design and implement an I/Q down-converter operating at 2GHz with CMOS 0.35-μ technology. I/Q down-conversion is an orthogonal frequency conversion from RF (IF) to base-band frequency. The down-converter is located in sequence after a low noise amplifier (LNA) for a direct conversion receiver. The mixer of the down-converter must satisfy the receiver-required performance in areas such as gain, noise, and IIP3. The LO-RF isolation of the mixer for a direct conversion receiver must be also considered to minimize mixer self-mixed offsets. A passive mixer with transmission gate MOS switches biased at the gate is presented to reduce the mixer self-mixed offsets.; I/Q down-converter uses two orthogonal phase LO signals which are critical to the channel phase and amplitude balance. Since the down-converter is a part of the receiver, the balance is important for receiver error performance. This balance problem comes from a phase shifter that divides the LO signal into two orthogonal phase signals. External tuning, the use of limiting amplifiers, and statistical averaging replace the conventional I/Q mismatched phase shifter. However, those methods involve power consumption and loss and limit IC pin-outs. A phase shifter that has less loss and is insensitive to the mismatch between R-C elements is introduced to achieve the amplitude and phase balance.; In order to compensate the loss of the mixer, a base-band amplifier is designed in which active loads are source-degenerated. This source-degeneration suppresses the noise generation from loads and bias circuits. The performance specifications of the base-band amplifier rely on the given receiver specification. By utilizing a cascading system analysis (receiver chain analysis), the gain and noise-thermal and flicker could be optimized to meet the system requirement.; A system analysis of the receiver for a WCDMA application precedes the circuit design. The design and analysis of each block circuits follow. The implementation and measurement of the I/Q direct down-converter are presented. The performance and feasibility of the I/Q direct down-converter are identified through measurement. More advanced approaches to improve the performance of the I/Q direct down-converter are discussed.