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High-speed CMOS digital pixel sensors

Posted on:2003-07-07Degree:Ph.DType:Dissertation
University:Stanford UniversityCandidate:Kleinfelder, Stuart ArminFull Text:PDF
GTID:1468390011480807Subject:Engineering
Abstract/Summary:
In this dissertation the author argues that CMOS image sensors using per-pixel ADCs and memory yield high pixel throughput and frame rates. To demonstrate this, two new CMOS image sensors with complete per-pixel ADC and 8-bit memory were designed, fabricated, and characterized, reaching previously unattained performance benchmarks of 10,000 frames/s and 1 giga-pixel/s throughput.; The first was a prototype aimed at infrared imaging applications. It was configured as a linear array with direct access to pixel sub-components, permitting detailed electrical measurements of pixel performance. Fabricated in a standard 0.35 μm CMOS technology, each 30 x 30 μm pixel contained over 100 transistors and included a sample and hold, a globally biased, cascoded current source, an 8-bit ADC with 8-bit dynamic memory, and a 16 tap (4 to 6+ bit), individually programmable current-mode DAC with 16-bit memory. It proved that over 1,000 frames/s operation would be practical in a full 2-D array.; The second was a complete 2-D array for visual imaging. Fabricated in a standard 0.18 μm CMOS process, each 9.4 x 9.4 μm pixel contains 37 transistors including a photogate and an 8-bit ADC with 8-bits of digital memory. The 352 x 288 pixel chip combines snapshot image acquisition, massively-parallel 8-bit signal conversion, fully digital pixel output, and on-chip power management. Readout of the digitized pixel data is over a 64-bit (8-pixel) wide bus at 167 MHz, or over 1.3 GB/s, using a single uninterrupted clock. It succeeded in reaching continuous ≥10,000 frames per second operation and sustained ≥1 giga-pixels per second throughput. Sensor fill factor was 15% and conversion gain was 13.1 μV/e− using a photogate. Power consumption was as low as 50 mW at 10,000 frames/s. At 1,000 frames/s, integral non-linearity was 0.22% over a 1 V range, RMS temporal noise using correlated double sampling was 0.15% and fixed pattern noise with CDS was 0.027% RMS. Tests of interference between digital and analog signals showed no discernable increase in noise when up to 100 array-wide conversions were performed and over 10 MB of data, at 1.3 GB/s, flowed through the focal plane during the acquisition of each image.
Keywords/Search Tags:CMOS, Pixel, Image, Over, Digital, ADC, Memory, Using
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