| The rapid pace of innovation of silicon processes is enabling the integration of an unprecedented amount of logic on a single silicon chip. Significant hurdles accompany the capability to create ever faster and smaller electronic systems, requiring the development of novel design methodologies. In this work, we explore one of those methodologies: Dynamic Packet Switched Networks-on-Chip (DPS-NoC). DPS-NoC technology can be used to standardize the cross-chip communication environment, allowing for a great deal of design flexibility, and decreasing the duration of the design cycle.; In this work, we discuss the architectural choices involved in creating a viable, DPS-NoC connected system of processing elements. We describe our experience leading a design team to the creation of a set of SoC style processing blocks, and a generic network infrastructure to connect them. We leverage this experience to discern the salient qualities of DPS-NoC interconnect, in order to better understand its place in the design landscape. With an understanding of the characteristics of such an interconnection system, we choose an application that is extremely difficult to implement with traditional ASIC point-to-point interconnect: Low Density Parity Code (LDPC) decoding. We then thoroughly explore the architecture of a DPS-NoC LDPC decoder, creating a set of parameterizable building blocks with which to construct the system. Next, we describe two modes of operation of the LDPC decoder system, and their implications to hardware size, complexity and performance.; We conclude with the observation that one of the most important features of DPS-NoC interconnect, flexibility in the face of variable communication patterns, makes it a perfect fit for a sub-domain of the ASIC design space: Application Specific Standard Products (ASSP). Such systems are focused enough in their functionality that the network can be sufficiently specialized to gain high performance, but require a high degree of runtime parameterization. We argue that systems that do not utilize the flexibility of DPS-NoC do not justify the expense of dynamic interconnect, making the application space a critical consideration. |
