Statistical analysis and optimization of process variation effects on circuit operation

Continued shrinking of semiconductor device dimensions has increased circuit sensitiveness to process variations which do not proportionally scale dowry with device geometries. These variations are inherent, in every manufacturing process, and cause manufactured parts differ from each other. Accurate modeling and optimization of the processes for critical circuit types and responses are, therefore, necessary during the initial stages of a new process design. In this dissertation, a technology computer-aided design (TCAD) driven method for true prediction of the spread of the performance of digital integrated circuits is proposed and demonstrated through simulations. A design-of-experiments (DOE) flow is first prototyped. The methodology starts with the development of the process recipe. Once acceptable device characteristics are obtained, transistor model parameters are extracted for circuit simulations, and test circuits are simulated for the nominal response. The nominal values of the process parameters are determined during this initial process development and device design. After completion of nominal value design, process variations are introduced to some of the process parameters using engineering estimates based on the process history. Screening experiments are designed to determine the relative effects of given process variations on circuit performance measures of interest such as the input-output delay and the average power dissipation. Critical process factors are identified by considering the correlation between input factors and output responses.; Once the critical process parameters are identified, two types of optimization methods are proposed. In the first method, process parameters are optimized for the desired circuit output. Response surface models (RSM) are generated to model different circuit responses as a function of process parameters. Process optimization is then performed using the RSM models developed to tune the circuit performance. Conflicting circuit performance measures are quantified, and a region of process input parameters, which meet various response conditions; is identified. In the second method, transistor design parameters are optimized in the presence of identical process variations considered in the first method.; This methodologies are demonstrated on circuits manufactured with a CMOS design flow. The work presented here maps the process space to design space and can play a key role in design for manufacturability (DFM) to quantify the effect of process variations on circuit design. This TCAD-driven method can be used at a very early stage of process development, when there is insufficient amount of electrical test data.