| To optimize circuit path delay, minimize clock skew, and reduce crosstalk noise, knowledge of process variations is necessary. The interconnect and device parameter variations in conventional circuit techniques are typically represented as random variables, but recent studies (especially when considering interconnect variation in chemical mechanical polishing (CMP) processes), have shown that strong spatial pattern dependencies exist. Therefore, the total variation can be separated into random and systematic components, where a significant portion of the variation can be modeled based on layout characteristics. In circuit simulation, key to reduce design uncertainty and maximize circuit performance are modeling the systematic components of different variation sources and implementing these effects. This thesis presents a methodology to incorporate systematic pattern dependent interconnect and device variation models for use with circuit extraction and simulation tools. Systematic models are implemented within a computer aided design (CAD) tool environment to enable automated analysis since the impact of variation is a function of circuit type, performance metric, type of technology, and type of variation source under consideration. |
