Multi-standard radio transceiver architectures and radio frequency front-end design

Handheld Wireless devices are becoming extremely popular as they continue to benefit from unprecedented levels of integration. They are becoming more and more compact achieving multi-functions and meeting a multitude of different wireless standards.; Great strides have been achieved with the digital baseband/Mac part of a portable handheld wireless solution while the big challenge confronting current and future wireless chipset development remains in the radio part having to achieve multi-band and multi-standard operation at low power consumption and very low bill of material.; The dissertation focuses on the development of new radio architectures for wireless applications and reports a configurable wireless radio receiver architecture and two configurable radio transceivers suitable for single chip integration. The new architectures are optimized to achieve maximum hardware share amongst the different wireless standards, while consuming minimum levels of power.; The receiver is intended for convergent EGSM, WCDMA and Wi-Fi applications. It is configured as a low IF receiver in the EGSM mode and as a zero-IF receiver for either the WCDMA or the Wi-Fi mode. One of the two transceivers developed in the dissertation is designed for Bluetooth, 802.11b, and 802.11a. In the Bluetooth mode, it operates as a low-IF and in the WLAN mode it operates as a zero-IF. The second transceiver achieves concurrent Bluetooth and Wi-Fi operation allowing one, for example, to browse the Internet with Wi-Fi while at the same time synchronize with others in the room with Bluetooth. This transceiver exploits Adaptive Frequency Hopping, originally introduced for the purpose of ensuring coexistence between Bluetooth and Wi-Fi, to achieve two objectives: (1) develop a new radio architecture with maximum hardware share and (2) de-multiplex Bluetooth and Wi-Fi signals at the transceiver front end.; The dissertation performs complete link budget analysis of all newly proposed radio architectures mapping system level requirements to the sub-system and block and circuit levels. The results are tabulated. Finally, we discuss design and experimental results of an RF front-end achieving design requirements within the performance ranges required by the radio architectures discussed in the dissertation. The design was done in a SiGe BiCMOS deep sub-micron technology.