| Complementary Metal Oxide Semiconductor (CMOS) technology has demonstrated promising future for low power and low cost digital/analog applications. Designers are currently utilizing the advanced deep submicron technology to achieve the goal of low voltage and high performance integration. However, addition of new material such as HfO2, nitrogen, difficulty in controlling the variations such as gate oxide growth, mismatches etc with smaller size and device degradation issues such as Negative Bias Temperature Instability (NBTI), Channel Hot Carrier (CHC), Time Dependent Dielectric Breakdown (TDDB) etc. in modern technologies has become significant compared to older technologies. Technology scaling has also resulted in greater sensitivity to Single Upset Transients (SUTs) in radiation intensive environment, can cause large transients which may lead to soft and hard errors. There- fore, reliability of both digital and analog circuits has become a serious issue in nanometer Very Large Scale Integrated (VLSI). The International Technology Road-map for Semiconductors (ITRS) explicitly calls for a fresh look on nano-architecture with emphasis on defect-tolerance. The effect of these degradations, variations and transient faults can cause unpredictable signal errors (i.e. errors in gain, phase, settling time and DC voltage etc.) and catastrophic faults in analog circuits. In this work, we have addressed these issues.;First, we designed and implemented ultra low power and small area on-chip NBTI sensors which can be used for accurately sensing the temporal degradation due to NBTI in ana- log circuits. We have shown that the temporal degradation in threshold voltage of p-type Metal Oxide Semiconductor (PMOS) transistor in analog circuits has high correlation to the variation of output voltage of proposed NBTI sensor.;Second, we have shown a systematic design methodology using voting based strategy for improving the reliability of analog and mixed mode circuits in presence of large transient errors and parametric variations.;Third, we have shown three different voting mechanisms for analog systems, i.e. based on majority, median and mean computation. At low redundancy factors , the majority voter can be implemented more efficiently.;Fourth, we proposed a design for reliability scheme, which is based upon the selective overdesign of the critical sections of the circuits and systems. |
