Testability Simulation Verification Technology And Software Development Of Analog Circuits

With the higher and higher integration of analog circuits, the testability verification test for analog circuits is particularly important. However, at present we still face many problems and difficulties in the testability verification test. Therefore, supported by provincial assembly pre-research project, this dissertation designs and develops testability verification software of analog circuits. And it conducts in-depth research on the overall design of the software and the implementation of the core modules. Meanwhile, it takes a specific circuit as an example for the test and verification of the entire system software. The main contents are as following.1.The design of the entire software program. According to the execution process of the testability verification test, the entire software is divided into four functional modules: the selection of test program, the allocation of fault samples, automatic emulation and fault diagnosis, parameter evaluation. Under VC6.0, combining Pspice simulation software with MySQL database, this dissertation designs the overall functional architecture of the software.2.In the current testability verification test, the test program is difficult to determine, the parameters are difficult to assess and the test remains error. Thus, based on in-depth research of the methods of test program and parameter evaluation, the two algorithms of success or failure fixed number sampling and the minimum acceptable value used by determining the test program are implemented. Moreover, several algorithms for parameter evaluation such as confidence interval estimation and one-sided confidence limit estimation etc are also achieved. At the same time, the dissertation also designs and implements an interactive graphics display interface for the test program’s selection module and parameter evaluation module.3.The cost and risk can’t be controlled on physical fault injection in the current testability verification test and the results of the test are incomprehensive and inaccurate. So, combining VC6.0 with Pspice, the dissertation develops an automatic fault injection platform in the way of simulation verification. Test results show that the developed platform not only improves the flexibility of fault injection, but also can simulate a variety of common faults.4. The functional modules of automatic simulation and fault diagnosis are implemented. This dissertation adopts the model files of associated circuits and the way by judging the size of simulation output files. And through those ways, it solves the following problems: It can’t achieve automatic simulation of specific types of devices when combining VC6.0 with Pspice; It is inefficient and easy to have application crashes when using the simulation output files to establish the fault dictionary automatically in VC6.0.And by constructing special string array, it realizes automatic conversion of the integer coding fault dictionary.5. The testability verification software of developed analog circuits has been tested and verified. Each functional module of the software and data exchange between modules are tested by using common band-pass filter circuit. Through test and verification, the software not only gives the desired results efficiently and accurately, but also solves the problems that the test program is difficult to calculate and parameter evaluation is difficult to develop in testability verification test.