| Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. Appropriate clocking strategies are imperative to keep the devices properly coordinated. These strategies have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems.; The conditions under which the optimal tradeoff between power and performance can be achieved have been derived. Models for the constraints associated with local and global clocking have been developed and validated. The impact on timing of power-supply noise and of interlevel coupling noise has been modeled and analyzed. Finally, promising new design strategies for future integrated systems have been proposed. |
