| Advanced transistor-level circuit design techniques can be used to increase the performance of digital systems. This thesis introduces new circuit configurations and associated clocking techniques that can achieve better performance than previous approaches.; In the first innovation, skew-tolerant domino circuit design is extended by including the complementary technique of enhanced precharge contention. This combined approach allows time borrowing to occur in both the forward and reverse directions, which results in faster circuits.; In a second technique, a new form of self-resetting CMOS is introduced which has improved robustness over process, temperature and voltage variations. This is achieved by using a logical structure, rather than a timing chain, to activate the evaluate and reset modes of a circuit. This enforces the correct sequencing of events under a wide range of operational and environmental conditions.; The above design methods are evaluated in some important applications. Specifically, high-speed adders, a multiplier, a CORDIC processor and a Viterbi ACS unit have been designed and simulated. Comparative results are presented which demonstrate the effectiveness of the proposed techniques.; Finally, a new framework for the analysis of self-resetting CMOS circuits is introduced. Performance metrics for five different circuit structures are constructed and verified. |
