Low jitter clocking of CMOS electronics using mode-locked lasers

The clock is the heart-beat of an electrical system. Most communication and processing functions in CMOS chips are triggered by a clock edge. An unstable clock can cause a system to fail or limit its frequency range of operation. Electrical clock signals are typically generated on-chip and distributed to end nodes through a symmetrical network of wires. As the number of end nodes has grown with Moore's Law scaling, the jitter and skew in electrical clock distribution have become a bottleneck to the speed of CMOS chips. Optical clocking is a radical approach in which a laser is used as the precision time source and optical distribution schemes are used instead of wire networks.; This dissertation investigates the feasibility and potential advantages of optical clocking. First, a comparative model is developed to assess the benefits and realm of applications for optical clocking in electrical systems. Next, experiments investigating the feasibility of injecting optical clocks into CMOS digital circuits are presented. Optical clock injection with hybrid detectors as well as monolithic CMOS detectors is demonstrated in this dissertation. Finally, a small scale demonstration of optical clock distribution is presented in the context of a high speed chip-to-chip link. In this demonstration we show that optical clock injection provides sub-picosecond clock jitter, and has the potential for sub-picosecond clock phase adjustment. The optical scheme provides a 3X reduction in clock jitter over an equivalent electrical scheme in this application.