The Research And Architecture Design Of H.264 Motion Estimation Algorithm

The next-generation video-coding standard, H.264 video compression standards, includes many advanced methods of video compression coding. Compared with previous video-coding standards, it has a significant progress that it is a more practical and efficient image-coding standard. The research and analysis about H.264 algorithm show that the computation of the motion estimation module in the algorithm is the largest. Whether in hardware or in software, the motion estimation occupies a very important position.The motion-estimation algorithm in H.264 standard has a high computational complexity, and can't easily achieve in real-time, so this paper presents architecture of data transmit of motion estimation. The structure can improve data throughput rate by greatly reduce the repeat of data read. In this paper, it used hybrid search algorithms, consisting of asymmetrical cross search, small-scale full-search, hexagon search, a small diamond search. According to the characteristics of each search algorithm, the paper presents an effective structure of a hardware implementation. In the design, it describes a high performance parallel-water processing structure. In the structure, it divides the four algorithms by 31 SAD processing units, combined with flexible RAM access mechanism, which can effectively achieve real-time image processing. Finally, the paper gives the results of design, simulation and verification on the motion estimation module using Verilog HDL language.Compared with traditional solutions, the structure is simple and easy to control; greatly reduces the gate resources; improves the parallel processing speed, and effectively achieves real-time processing. The results of the FPGA simulation show that the design can meet the real-time processing requirements of HD video.