A multibit cascaded sigma-delta modulator with DAC error cancellation techniques

Noise reduction techniques are developed for a multibit cascaded sigma-delta modulator used in the analog interface of a digital processing system to improve its performance by reducing the errors introduced by digital-to-analog converters (DACs). The idea of the proposed architecture is to create extra feedback paths around the modulator to shape the DAC errors further by the properly selecting the error cancellation logic. Transfer functions show that the DAC error at the final stage of the proposed architecture is totally cancelled while its DAC errors from other internal stages are shaped by an order higher than those in a conventional cascaded modulator.; The difficulty in circuit implementation of modulators with high resolution and bandwidth increases due to the imperfection of analog components in VLSI processes. Structural and circuit-level compensation techniques are usually used in developing such modulators. Major analog nonidealities in a multibit cascaded sigma-delta modulator include coefficient mismatches, DAC nonlinearity errors, and integrator leakages. While providing solutions for each of these nonidealities, this dissertation focuses on the minimization of the DAC error since it causes the most performance deterioration.; A configurable fourth-order (2-1-1) sigma-delta modulator is implemented for architecture verification. This modulator can be configured as the proposed architecture as well as a conventional cascaded structure with various modulator orders. Design of the system's parameters and analog blocks are well described in this dissertation. The designed system is fabricated by AMI 0.5mum double-poly triple-metal mixed-signal process through MOSIS. Measurement results show that with on-chip error of +/-3.2% LSB for each DAC and an OSR of 32, an improvement of 8dB of the proposed architecture over the conventional structure is observed.