Modeling and design techniques for improved delay, power and signal integrity in nanoscale VLSI

The scaling of integrated circuit (IC) technologies to the nanometer regime has resulted in various nanometer scale effects such as interconnect delay, cross-coupling, on-chip inductance, signal integrity, leakage power dissipation, process variation, and yield degradation. These effects can have an adverse impact on integrated circuit performance, power consumption and reliability. These nanometer effects will continue to get worse in future technologies and are expected to become a limiting factor in CMOS (Complementory Metal Oxide Semiconductor) scaling.; This dissertation concentrates on interconnect, leakage power and process variation related issues in nanometer IC design. The dissertation makes two fundamental contributions regarding these issues. First, advanced modeling solutions are developed that enable integration of these effects in the IC design flow. Second, novel design approaches are proposed to minimize the negative impact of these effects on circuit performance and reliability.; A main component of the dissertation focuses on interconnect modeling and design. Efficient closed form interconnect models are developed for timing and noise driven physical design optimization tools. The impact of back-end process variations on interconnect performance is investigated and efficient statistical interconnect models are proposed. The dissertation also focuses on modeling self and mutual inductive effects in on-chip interconnects. A coupling noise model and a gate output waveform model for on-chip RLC interconnects are developed. From a design perspective, a technique to deal with signal integrity issues called dynamic clamping is proposed. This approach is effective in reducing noise and inductive effects in high-speed RLC global buses. A technique called optimal inductance is also developed that reduces the delay of global interconnects by exploiting the faster transition times observed due to inductance.; In addition to interconnect issues, this work also addresses the issue of growing leakage currents and their impact on future device scaling. Novel design solutions are proposed that can be used to reduce leakage power consumption without trading off performance. Various global signaling approaches targeted towards reducing leakage in power hungry repeaters are discussed. It is shown that the proposed skewed pulsed bus configuration can provide nearly 25% reduction in active mode leakage and 99X reduction in standby mode leakage while enabling ∼20% improvement in performance.; Finally, process variation and its impact on parametric yield is analyzed. An analytical model is developed that can be used to predict parametric yield under given power and frequency requirements. The proposed model is then used for optimal supply voltage selection that results in yield maximization.