Cost Effective Error Detection for SoC Validation and Online Testing

Error detection is the vital component of the quality assurance tasks during the life time of an integrated circuit to avoid costly in-field failures and massive product recall. Nevertheless, sufficiently thorough error checking requires the development of high quality tests and on-chip checkers that can themselves be very expensive. How to detect all the errors while minimizing the cost remains one of the most challenging and critical questions for the semiconductor research community. This dissertation attempts to address this issue by proposing several cost effective error detection techniques targeting the stages of post-silicon validation and online testing. First, a time-multiplexed checking scheme is proposed to accommodate on-chip hardware checkers with low overhead. The same hardware resource for checker implementation can be used as a design-for-debug (DfD) structure for post-silicon debugging and later reused as a design-for-testability (DfT) resource during online testing. Case studies and mathematical analyses demonstrates the schemes provide high error coverage and a significant reduction in chip area and power overhead for on-chip checkers at the cost of increased fault detection latency. Second, a series of test evaluation metrics are proposed based on error models of electrical bugs and data mining based fault-model-free approach. Experimental results demonstrate that the intelligent navigation of validation test plan based on relevant bug model or knowledge mined from post-silicon test data can prioritize those tests capable of uncovering more silicon timing errors, resulting in significant reduction of validation time and effort.