Continuum and sub-continuum thermal modeling of electronic devices and systems

Ever increasing demand for faster microprocessors and the continuous trend to pack more transistors on a single chip result in an unprecedented level of power dissipation. As an additional complication to the surge in power consumption of microprocessors, non-uniformities of power distributions across chips further drive up the on-chip peak temperatures and affect microprocessors reliability and performance. While the global power and temperature distribution of microarchitectures have received much attention, nanoscale thermal effects within individual transistors have imposed different challenges to device designers. As transistors are scaled to dimensions comparable to, or less than, the mean free path of heat carriers in silicon, i.e. phonons, it is essential to study in detail the scaling physics, which involves a more comprehensive understanding of phonon transport at small scales.; This work aims at investigation of multi-scale thermal phenomena from transistor to chip levels. A novel analytical approach based on two-dimensional frequency domain analysis of heat transfer is presented to address/investigate the outstanding issues related to the non-uniform chip power and temperature distributions. Using this method, the concept of a transfer function for single and multi-layer packages in the frequency domain is defined. The behavior of this transfer function that represents the thermal response of a chip to different frequencies of dissipated power is studied in order to obtain appropriate power granularities for microprocessor power models as well as the impact of various components of packages on heat removal from chip hotspots. Furthermore, a frequency-domain analytical/numerical approach was developed that yields the temperature distribution in single and multi-layer geometries relevant to rapid thermal modeling of advanced microprocessors. It was shown that the performance of this approach can be 3 orders of magnitudes higher than that of conventional space domain approaches such as the finite element method.; This work also investigates the effect of scaling on thermal behavior of deep sub-micron SOI transistors and nanostructures. Electrical and thermal characteristics of current and future generations of silicon-on-insulator transistors with gate lengths from 180 nm to 45 nm have been examined through elaborate electro-thermal simulations while sub-continuum thermal effects and short channel effects are taken into account. Furthermore, the effect of scaling on temperature rise at, and in the vicinity of, nanostructures with dimensions as small as 100 nm were obtained experimentally. The results indicate that the non-equilibrium localized heating is insignificant at the present scales.