Design and analysis of jitter-tolerant digital delay-locked loops and fixed delay lines

The last five decades have witnessed dramatic improvements in integrated-circuit performance and a steady migration towards more complex standard-cell-based digital designs. As clock frequencies continue to increase, and noise and timing margins decrease, there is rising demand for synchronization circuits that can operate in the presence of noise and jitter and can be easily ported among different integrated-circuit technologies. To address these challenges, this research focuses on improving the noise and jitter tolerance of two essential timing circuits: the digital delay-locked loop (DLL) and the fixed delay-line (FDL). Several analytical models are introduced to provide a complete set of tools for analyzing DLL and FDL behavior, including both continuous and discrete-time models that more accurately predict nominal performance, and a Markov-chain-based stochastic model that predicts worst-case performance.; To address the issues of noise and jitter tolerance, a standard-cell-based digital DLL architecture is introduced that has reduced sensitivity to jitter on the reference signal. The proposed architecture uses a three-state phase detector that is scaled with the master delay chain to improve jitter tolerance without sacrificing tracking accuracy or bandwidth. Alignment circuitry is also included to continually center the reference clock in the phase-detector window and reduce jitter-induced toggling. Simulations of the proposed design predict a 76% reduction in jitter sensitivity when the reference signal has a Gaussian jitter distribution with a standard deviation of two delay steps.; A fixed delay-line (FDL) using the same basic jitter-tolerant architecture is also presented. Two versions of the FDL, 1/4 and 1/8 cycle, are implemented in the memory interface section of a 0.13-mum CMOS digital television chip. The measured worst-case delay variation of the 1/4 cycle delay line is two delay steps, which is a factor of three lower than the simulated variation for a conventional FDL under the same conditions. Jitter-induced toggling is also reduced by more than an order of magnitude.