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Clock programmable IF circuits for CMOS software defined radio receiver and precise quadrature oscillators

Posted on:2007-08-23Degree:Ph.DType:Dissertation
University:University of California, Los AngelesCandidate:Mirzaei, AhmadFull Text:PDF
GTID:1448390005965325Subject:Engineering
Abstract/Summary:
The proliferation of bands, modulation formats and standards in wireless communications calls for a universal software-defined receiver (SDR) and transmitter. This digitizes the received waveforms as soon as possible to relegate as much functionality as possible to digital signal processor (DSP). The channel of interest varies from tens of KHz to tens of MHz located anywhere in the 800-MHz to 5-GHz spectrum. Traditionally, an SDR receiver is defined as one where the only analog component is an RF AID converter which digitizes the whole spectrum right at the antenna. Thus, all radio functions are realized in a programmable digital signal processor. However, to digitize all possible signals incident on the receiver, a 12-b, 12-GHz ADC is required which is not within the performance of today's ADCs.; Instead, to digitize the signal using the low-cost ADCs, we envisage the SDR receiver as a signal conditioner which emphasizes the desired channel and de-emphasizes the rest. Channel selection is partially performed in analog domain and mainly accomplished in digital domain with sharp FIR channel selection filters. The approach relaxes the analog filter, which should then only attenuate interferers to the extent that ADC can resolve the wanted signal and residual interferes without being overloaded. This filter must also provide strong anti-aliasing at ADC sampling frequency and its integer multiples and should have clock-programmable cutoff frequency over orders of magnitude. Majority of this work is to design and implement such anti-aliasing pre-filters.; The rest of this work is dedicated to generate accurate and low-noise quadrature signals. The conventional quadrature oscillator (QOSC) is modified by inserting phase-shifters between the two oscillator cores. Based on the two novel analytical approaches, geometrical/phasor-based and injection pulling/locking, it is verified that the modified QOSC has a single-mode oscillation with zero or minimum sensitivity to mismatches. The presented modified QOSC has also less phase-noise compared to the conventional design without phase-shifters as well.; Finally, the idea of progressive multiple mode injection in ring oscillator injection-locked dividers is introduced to widen their lock-range. Based on this idea, we present quadrature-balanced injection-locked dividers with wide lock-range.
Keywords/Search Tags:Receiver, Quadrature, SDR, Oscillator
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