Design Of Energy-efficient Class-C Quadrature Voltage Controlled Oscillator

With the growth of the rapid development of information,the rate requirements for data transmission interfaces are constantly increasing.The application scenarios of high-speed serial interface circuits using SERDES technology are more and more extensive.In the interface circuit of the SERDES structure,the design of the clock data recovery circuit(CDR)in the RX plays a decisive role in the entire system,it directly determines the energy utilization rate of the entire high-speed interface.The voltage controlled oscillator(VCO)as a key module in the CDR circuit,It is of great significance to study how to improve its comprehensive performance.The design goal of this thesis is to design a quadrature VCO used in a half-rate CDR circuit with a rate of 10Gb/s based on the TSMC 40nm CMOS process.In order to improve the Fo M of the oscillator,the VCO designed in this thesis works in class C to improve the current utilization of the circuit.The overall circuit uses an improved dynamic bias feedback loop structure to overcome the contradiction between the start-up and amplitude of the Class C voltage-controlled oscillator.By adding an RC low-pass circuit in parallel with the transmission gate in the feedback loop,as the oscillator starts to oscilate,the transmission gate is opened and the RC low-pass circuit is shorted.As the swing of the output signal of the oscillator increases,the output voltage of the feedback loop decreases.When the output voltage is lower than the preset voltage of the negative terminal phase of the comparator,the transmission gate is turned off.It can reduce the impact of the feedback loop noise and output fluctuations on the oscillator circuit performance.The quadrature oscillator uses a capacitive source degeneration coupling structure.This structure can provide additional negative resistance to the oscillator to help the Class C oscillator start.The structure can also bring a phase shift to the coupling path to reduce the deterioration of the Fo M of the oscillator.The post-simulation results show that,under 1.1V supply voltage,the area of the oscillator designed in this thesis is 0.29mm~2,power consumption is 3.83mW,the differential swing amplitude is about 760mV,the frequency coverage is 4.62GHz to 5.35GHz,and the phase noise of the oscillator at 1MHz is-120.4dBc/Hz,and the Fo M of the circuit is188.4dBc/Hz.The oscillator can also output a stable quadrature signal.