Architecture and design methodology for power gated programmable fabrics

Under shrinking dimensions of feature size and power supplies, FPGAs have evolved from a mere prototyping or glue-logic unit to a viable platform for system level implementation. As fabrication technology has already touched the 65nm technology node, programmable fabrics are facing some of the daunting challenges such as, exponential increase in leakage current, decreased noise margin, reliability and narrow-width effects etc. Increase in leakage current is by far the most serious issue in ultra deep sub-micron designs due to the inherent power hungry architecture of FPGAs. The flexibility to implement various designs in the same piece of silicon results in massive under-utilization of FPGA resources in the spatial and temporal domain. These under-utilizations lead to standby power dissipation even if the transistors are completely inactive and have no meaningful output. The dependence of static power on temperature has also underscored its importance in nanometer designs. As we go further towards smaller process geometries, transistor packing density increases manifolds. This results in increased junction temperature and the possibility of a positive feedback loop between leakage current and temperature. Such interactions pose a serious threat to the reliability of a circuit.;Power management in programmable fabrics has become a necessity in technologies below 100 nm. So far, power consumption has been a major hurdle in such architectures to explore territories like mobile and portable applications. FPGA fabric needs a paradigm shift in the architecture and CAD tools so that power stringent applications can be implemented in a programmable device.;In this dissertation, we present a leakage tolerant architecture and design methodology to tackle static power dissipation for FPGA design flows. We show a new design methodology for reducing leakage power by exploiting temporal idleness in designs and accordingly group them into clusters that can be switched on and off depending upon their activity. We also propose a new Power State Controller (PSC) based MTCMOS FPGA architecture to mitigate static power dissipation. We have carried out detailed experiments and analyses to find out various trade-offs among important design variables like performance, active leakage, standby leakage, dynamic power, area etc. Based on our in-depth analyses we have proposed an optimal granularity at which leakage has to be controlled for proper trade-offs among these variables. Another focus of this dissertation is to develop an FPGA architectural exploration tool that gives fast estimates of the design metrics and allows us to gauge the effect of leakage aware CAD algorithms on such architectures. The tool is very flexible, in that it can estimate the leakage control granularity and the overhead for a wide variety of FPGA architectures. As the tool is event driven, it does not require extensive simulation, hence can be used to explore a large architectural design space. We also present in this dissertation, a power-aware floorplanner that adapts perfectly into such architectures so that maximum number of FPGA resources can be shut down at any given time.