Circuit modeling for signal integrity in advanced VLSI technologies

Signal integrity analysis is one of the crucial analysis steps in designing a high performance microprocessor. Crosstalk can induce a logical failure or cause excessive signal delay resulting in performance degradation. Typical parts of signal integrity analysis are: circuit modeling and interconnect modeling. This dissertation examines the deficiencies in modeling of the receiver circuits for SOI and bulk CMOS nanometer technologies. The receiver circuit noise immunity determines if a particular interconnect violates the signal integrity requirements. Inadequate modeling of receiver circuit noise immunity therefore has direct bearing on the number of false violations reported and the number of true violations filtered. We propose a wave-fitting crosstalk modeling technique suitable for nanometer designs which improves the receiver characterization used in crosstalk analysis. We propose modifications to current crosstalk analysis techniques to account for multiple noise events at the receiver inputs which can lead to lowering of receiver noise immunity. We demonstrate that PD-SOI is more crosstalk sensitive than comparable bulk CMOS technologies and propose analysis techniques that account for the floating body terminal in PD-SOI receiver circuits. We also investigate crosstalk susceptibility in sub-threshold circuit operation as low power applications increasingly utilize sub-threshold operation to reduce power. We propose empirical models for off-state power and leakage current in PD-SOI which accounts for input switching history. The off-state power can be 2.4x the expected power due to the floating body terminal in PD-SOI. We demonstrate the practicality of all our proposed receiver models and crosstalk analysis techniques by using industrial microprocessor core designs in nanometer technology as test cases.