Floating-point unit design using Taylor-series expansion algorithms

Due to the constant advances in VLSI technology and the prevalence of many applications that require floating-point operations, hardware support for floating-point arithmetic is an essential feature in high-performance computer systems, embedded systems as well as mobile applications. Over the past years, while addition and multiplication implementations have become increasingly efficient, support for division and other elementary functions such as square root has remained uneven. Although division and square root are relatively infrequent operations in traditional general-purpose applications, they are indispensable and becoming increasingly important, particularly in many modern applications. Furthermore, as the latency gap between addition/multiplication and division/square root grows, the latter operations increasingly become performance bottlenecks. Therefore, poor implementations of floating-point division and square root can result in severe performance degradation.;This dissertation presents various techniques for designing an area-efficient yet high-performance floating-point arithmetic unit using a high-order Taylor-series expansion algorithm with truncated powering units. First, we propose a floating-point divider unit based on a 3rd-order Taylor-series expansion algorithm with truncated powering units. This algorithm achieves fast computation by using truncated powering units, which compute the higher-order terms in the Taylor-series polynomial significantly faster than traditional multipliers with a relatively small hardware overhead. Through careful pipeline design, all multiply operations required by the division algorithm and floating-point multiply operations are executed by one multiplier to maximize area efficiency while achieving high performance. Second, we expand the algorithm and present a generalized floating-point divider design procedure using high-order Taylor-series expansion algorithms by exploring the trade-off space of design constraints for a given precision, which is necessary for an efficient implementation of a divider. Third, we extend the proposed floating-point divider to incorporate square root. Since Taylor's theorem enables us to compute approximations for many well-known functions, we can extend the proposed divider unit to incorporate a square root function. And due to the similarity between the Taylor-series approximations of these functions extending the existing divider to incorporate square root can be achieved with little area and latency overhead. Finally, this dissertation provides insight into trade-offs involving overall FPU organization alternatives using the proposed floating-point divider. Several design considerations and trade-off factors in floating-point unit implementation are evaluated for two types of FPU architectures optimized under different design goals.;The proposed arithmetic unit exhibits area efficiency as well as high performance required by many modern floating-point intensive applications such as scientific computing, CAD tools and 3D graphics rendering, which have a high percentage of division and square root operations.