| The choice between Nyquist-rate and oversampling analog-to-digital converters for high-speed applications has been primarily based on the resolution, with the dividing line lying around 14 bits. At the 14-bit level, therefore, the two classes exhibit competitive attributes - but different trade-offs as the device dimensions and supply voltages scale. This research demonstrates that oversampling ADCs can indeed compete with and even supersede their pipelined counterparts at the 14-bit level. This work proposes a low-complexity DAC mismatch shaping technique that lends itself to low oversampling ratios (OSRs), leading to an ADC having a measured SNDR of 70 dB at an analog input frequency of 31 MHz, the highest combination reported in the literature in CMOS technology for a power dissipation of 140 mW. The design also achieves a dynamic range of 80 dB at 31 MHz, the highest combination reported for Sigma Delta modulators. While applied to a discrete-time modulator here, the mismatch shaping technique can be utilized in continuous-time implementations as well. |
