Design optimization of ultra-scaled transistors and the impact of process variations

This dissertation investigates the effects of gate line edge roughness (LER) in short-channel MOSFETs and addresses issues in design optimization of symmetric ultra-thin double-gate transistors.; Poly-silicon gate LER is a process-induced variation of increasing concern for ultra-scaled MOSFETs. It causes variations in device gate length along its width and induces local CD (average gate length) spread. Because roughness is transferred to source/drain (S/D) to channel junctions by self-aligned implants, which is also subjected to modification of implantation scattering and dopant diffusion, the off-state current (IOFF) is particularly sensitive and increases significantly with gate LER. Depending on the spatial-frequency properties, estimating the LER effect on the IOFF requires either two-dimensional (2D) or three-dimensional (3D) device simulations. High frequency (HF) and low frequency (LF) LER affect S/D-channel junctions differently. 3D process simulations predict enhanced lateral diffusion and additional channel shortening for HF LER. The use of a scanning electron microscope (SEM) allows the characterization of poly-silicon LER on wafers. The correlation lengths are found around 30nm. Modest IOFF degradation is demonstrated on NMOS devices with significantly raised gate LER in controlled experiments.; The advantages of the symmetric ultra-thin body double-gate (SUTBDG) configuration make it a strong candidate for future MOSFET structures in low power applications, in spite of several remaining challenges. The device is sensitive to body thickness variations. Extrinsic parasitics limit device performance. They can be modeled analytically in 2D. The S/D structures can be optimized for maximum switching speed by trading-off the parasitics. With a fully controlled gate work function, we can take advantages of weakly-coupling S/D structures and relatively thicker bodies. Suppressing the fringing field induced barrier lowering effect caused by using of high-k gate dielectric requires significant equivalent oxide thickness (EOT) reduction or gate work function shift. Metal S/D SUTBDG devices behave differently from doped S/D devices due to their special transport mechanisms through S/D Schottky contacts. By considering the effects of parasitics, we predict that sub-100meV S/D Schottky barrier heights (SBHs) are required for metal S/D devices with gate lengths around 20nm to outperform doped S/D devices with similar dimensions.